NVLink-C2C is a chip-to-chip interconnect developed by NVIDIA for connecting processors, GPUs, and other accelerators within a single system. It is based on the NVLink protocol, which was first announced in March 2014 as a wire-based serial, multi-lane, near-range communications link. Unlike PCI Express, NVLink allows devices to use multiple links and mesh networking, enabling direct peer-to-peer communication without a central hub. NVLink-C2C extends this technology to provide high-bandwidth, low-latency connections between different types of chips, such as a CPU and GPU, or between multiple GPUs in a tightly coupled system. This interconnect is critical for modern AI and machine learning workloads, where massive data transfer between compute elements is required.
NVLink-C2C supports coherent memory sharing, allowing connected devices to access a unified memory space. This simplifies programming and reduces data duplication, improving performance for applications like deep learning and large language models. The technology is used in NVIDIA's Grace CPU and Hopper GPU architectures, enabling systems like the Grace Hopper Superchip, which pairs a CPU and GPU over NVLink-C2C for accelerated computing.
Technical Specifications
NVLink-C2C leverages the physical layer of NVLink, which specifies point-to-point connections with data rates of 20, 25, and 50 Gbit/s per differential pair for versions 1.0, 2.0, and 3.0+, respectively. For NVLink 1.0 and 2.0, eight differential pairs form a sub-link, and two sub-links (one for each direction) form a link. Starting with NVLink 3.0, only four differential pairs form a sub-link. The total data rate per sub-link is 25 GB/s for NVLink 2.0 and higher, and the total per link is 50 GB/s. NVLink-C2C uses similar high-speed signaling but is optimized for chip-to-chip connections within a package or on a board, rather than between separate modules.
For example, the Grace CPU has 18 NVLink-C2C links, providing up to 900 GB/s of bidirectional bandwidth to a Hopper GPU. This high bandwidth enables efficient data movement for generative AI and transformer models, which require large memory footprints and frequent communication between compute units.
Architecture and Design
NVLink-C2C is designed to support a variety of topologies, including point-to-point, mesh, and switch-based connections. For small numbers of devices, direct links provide all-to-all connectivity. For larger systems, NVLink switches (introduced in 2018) use packet-switched architecture, with each switch supporting up to 32 two-lane ports. The NVSwitch for NVLink 4.0 includes the SHARP accelerator, which can perform simple computations like sum and broadcast in the network, reducing communication overhead.
NVLink-C2C also incorporates features for reliability and power efficiency. It uses a 128b/130b line code, similar to PCI Express 3.0 and higher, which reduces overhead compared to older encoding schemes. The physical layer includes link control characters and transaction headers, which add some overhead, but benchmarks show achievable transfer rates of about 90-95% of the theoretical maximum. For instance, a 40 Gbit/s NVLink connection to a P100 GPU achieved approximately 35.3 Gbit/s in real-world tests.
Applications and Use Cases
NVLink-C2C is primarily used in high-performance computing and AI data centers. It is a key component of NVIDIA's DGX systems, which integrate multiple GPUs for training and inference of large models. The interconnect is also used in the Grace Hopper Superchip, which combines a 72-core Grace CPU with an H100 GPU, delivering up to 900 GB/s of bandwidth between them. This design is particularly effective for memory-bound workloads, such as neural networks and large language models, where data transfer speed is a bottleneck.
In addition to AI, NVLink-C2C is used in scientific computing, where simulations and data analysis require high-throughput communication. The technology is also being adopted by cloud providers like Amazon Web Services and Google Cloud for their AI infrastructure, as well as by TSMC-manufactured chips in systems from AMD and Intel that incorporate NVLink-C2C for heterogeneous computing.
Comparison with Other Interconnects
NVLink-C2C competes with other high-speed interconnects such as PCI Express, CXL, and InfiniBand. Compared to PCIe, NVLink-C2C offers higher bandwidth and lower latency, as it is designed specifically for chip-to-chip communication rather than peripheral expansion. For example, PCIe 5.0 provides 32 GT/s per lane, while NVLink 4.0 offers 50 Gbit/s per differential pair, and with more links, total bandwidth is significantly higher. CXL, which is based on PCIe, supports cache-coherent memory sharing but typically has lower bandwidth than NVLink-C2C.
NVLink-C2C also differs from network interconnects like InfiniBand, which are used for system-to-system communication. NVLink-C2C is for intra-system connections, providing lower latency and higher bandwidth than network solutions. This makes it ideal for tightly coupled compute nodes in a single server or rack.
Future Developments
NVIDIA continues to evolve NVLink technology. NVLink 6, used in the Vera Rubin NVL72 platform, provides 3.6 TB/s of bidirectional bandwidth per GPU. An NVL72 rack uses nine NVLink 6 switches to deliver 260 TB/s of total scale-up bandwidth. These advancements are expected to support even larger AI models and more complex simulations, maintaining NVLink-C2C's position as a leading chip-to-chip interconnect in the industry.
As of 2025, NVLink-C2C is a critical enabler for AI infrastructure, and its adoption is growing across AWS, Azure, and Oracle Cloud offerings. The technology is also being explored for use in edge devices and automotive applications, where high-bandwidth, low-power interconnects are essential.