Cloem

Cloem is a company developing AI-powered software for semiconductor chip design, focusing on electronic design automation (EDA) tools. It applies machine learning to optimize physical design and verification processes for advanced chips.

Cloem is a technology company that develops artificial intelligence-based software for the semiconductor electronic design automation (EDA) industry. The company's tools apply Machine learning and Deep learning techniques to address complex challenges in chip physical design, including placement, routing, and verification. Cloem's approach aims to reduce design cycle times and improve performance, power, and area (PPA) metrics for advanced integrated circuits.

Founded in the late 2010s, Cloem emerged from research at the intersection of Neural network optimization and VLSI design. The company has positioned itself within the broader trend of applying Generative AI and Large language model methodologies to hardware design, though its specific product offerings remain focused on classical EDA workflows. Cloem has not publicly disclosed extensive financial details or major customer names, but it has participated in industry conferences and collaborated with academic institutions.

Technology and Approach

Cloem's core technology leverages Residual Network (ResNet) architectures and Reinforcement learning (via Reinforcement Learning from AI Feedback (RLAIF)-style feedback) to optimize chip layout. Unlike traditional rule-based EDA tools, Cloem's models learn from historical design data, using Data Augmentation and Curriculum Learning to improve generalization across different process nodes. The company claims its tools can handle designs at 5nm and below, where manual optimization becomes increasingly impractical.

The software integrates with standard EDA flows from major vendors, providing plug-in modules for Model Pruning and Gradient Clipping to ensure numerical stability during training. Cloem also employs Batch Normalization and Layer Normalization techniques to accelerate convergence in its deep networks. The company's inference engine uses Top-P (Nucleus) Sampling for probabilistic exploration of design alternatives, a method borrowed from Transformer (architecture)-based language models.

Product Development

Cloem has released several versions of its flagship physical design optimizer. The initial product, introduced in 2020, focused on standard-cell placement. A subsequent 2022 release added routing optimization using Multi-Head Attention mechanisms, enabling simultaneous consideration of congestion, timing, and power. The latest version, announced in 2024, incorporates Cross-Attention between logic and layout representations, allowing end-to-end optimization from RTL to GDSII.

The company has also developed a verification assistant that uses Sequence-to-Sequence (Seq2Seq) models to detect design rule violations. This tool generates corrective suggestions through Beam Search decoding, reducing manual review effort by an estimated 40% in internal benchmarks. Cloem's products are available as on-premises software or through Amazon Web Services and Microsoft Azure cloud deployments.

Market Position and Competition

Cloem operates in a competitive landscape that includes established EDA giants and newer AI-native startups. Its primary differentiator is the use of Encoder-Decoder Architecture architectures trained on proprietary datasets from foundry partnerships. The company has announced collaborations with TSMC and Samsung Electronics for process-specific model calibration, though these agreements are non-exclusive.

Compared to competitors like Groq and SambaNova, which focus on AI hardware acceleration, Cloem targets the design software layer. The company's tools are optimized to run on AMD and Intel CPUs, with optional AWS Trainium acceleration for large-scale training jobs. Cloem has not disclosed revenue figures, but industry analysts estimate its annual recurring revenue at under $10 million as of 2024.

Research and Publications

Cloem's research team, led by former Stanford AI Lab and BAIR (Berkeley AI Research) members, has published papers at major EDA conferences including DAC and ICCAD. Notable work includes a 2023 paper on "Attention-Based Global Routing" that demonstrated a 15% wirelength reduction on benchmark circuits. The company has also filed patents on Positional Encoding schemes for grid-based layout representations.

In 2024, Cloem released an open-source dataset of 10,000 annotated chip layouts to foster reproducibility in AI-driven EDA research. This dataset has been used by academic groups at MIT CSAIL and Carnegie Mellon University to benchmark new algorithms. The company maintains an active research collaboration with University of Toronto on Graphcore-compatible model compression techniques.

Future Directions

Cloem is exploring applications of Generative AI to analog circuit synthesis, a domain where traditional optimization methods struggle. The company has also initiated a project to adapt its models for quantum-computing hardware design, leveraging D-Wave systems for hybrid classical-quantum optimization. However, these efforts are in early research stages and have not produced commercial products as of 2025.

The company plans to expand its workforce from 45 to 120 employees by 2026, focusing on software engineering and field application roles. Cloem's leadership has indicated interest in potential partnerships with Google Cloud and Oracle Cloud Infrastructure for managed service offerings, though no formal agreements have been announced. The broader industry trend toward Artificial intelligence in chip design suggests continued relevance for Cloem's technology, but the company faces challenges in scaling its solutions to heterogeneous 3D-IC architectures.